1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the control of a shared cache memory within a data processing system.
2. Description of the Prior Art
It is known to provide data processing systems with multiple levels of cache memories. For example, a system incorporating multiple transaction sources, such as multiple processor cores, may provide a local cache memory dedicated to each of these transaction sources and a shared. cache memory that is shared between the transaction sources. For example, an individual processor core may have its own level one (L1) cache, a tightly bound cluster of processor cores may share a level two (L2) cache above the L1 caches in the hierarchy and finally a level three (L3) cache may be shared between the clusters of processors.
It is known to operate such cache hierarchies in an inclusive mode in which an individual cache line of data may stored in more than one cache within the cache hierarchy. This provides for more efficient data sharing but has the disadvantage of consuming more cache storage capacity. Another mode of operation of cache hierarchies is a non-inclusive mode (an exclusive mode). In this mode a given cache line of data is normally stored in only one cache memory of the cache hierarchy. This reduces the amount of cache storage used but is less efficient for data sharing.